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m28256 256 kbit (32kb x8) parallel eeprom with software data protection preliminary data january 1999 1/21 this is preliminary information on a new product now in developmentor undergoing evaluation . detail s are subject to change without notice. ai01885 15 a0-a14 w dq0-dq7 v cc m28256 g e v ss 8 figure 1. logic diagram 28 1 pdip28 (bs) plcc32 (ka) a0-a14 address input dq0-dq7 data input / output w write enable e chip enable g output enable v cc supply voltage v ss ground table 1. signal names fast access time: 90ns at 5v 120ns at 3v single supply voltage: 5v 10% for m28256 2.7v to 3.6v for m28256-xxw low power consumption fast write cycle: 64 bytes page write operation byte or page write cycle enhanced end of write detection: data polling toggle bit status register high reliability double polysilicon, cmos technology: endurance >100,000 erase/write cycles data retention >10 years jedec approved bytewide pin out address and data latched on-chip software data protection description the m28256 and m28256-ware 32k x8 low power parallel eeprom fabricatedwith stmicroelectron- ics proprietary double polysilicon cmos technol- ogy. tsop28 (ns) 8 x13.4mm 28 1 so28 (ms) 300 mils
a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 a14 v cc ai01886 m28256 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin connections ai01887 a13 a8 a10 dq4 17 a0 nc dq0 dq1 dq2 du dq3 a6 a3 a2 a1 a5 a4 9 w a9 1 a14 a11 dq6 a7 dq7 32 du v cc m28256 a12 nc dq5 g e 25 v ss figure 2b. lcc pin connections warning: nc = not connected, du = don't use. a1 a0 dq0 a5 a2 a4 a3 a9 a11 dq7 a8 g e dq5 dq1 dq2 dq3 dq4 dq6 a13 w a12 a6 a14 v cc a7 ai01889 m28256 28 1 22 78 14 15 21 v ss a10 figure 2d. tsop pin connections dq0 dq1 a3 a0 a2 a1 a10 e a13 dq7 g dq5 v cc dq4 a9 w a4 a14 a7 ai01888 m28256 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 dq2 v ss a6 a5 dq6 28 27 26 25 24 23 a11 dq3 1 a12 a8 figure 2c. so pin connections 2/21 m28256
symbol parameter value unit t a ambient operating temperature (2) 40to85 c t stg storage temperature range 65 to 150 c v cc supply voltage 0.3 to 6.5 v v io input/output voltage 0.3 to v cc +0.6 v v i input voltage 0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (3) 4000 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. depends on range. 3. 100pf through 1500 w ; mil-std-883c, 3015.7 table 2. absolute maximum ratings (1) ai01697 address latch a6-a14 (page address) x decode control logic 256k array address latch a0-a5 y decode v pp gen reset sense and data latch i/o buffers egw page load timer status toggle bit data polling dq0-dq7 figure 3. block diagram 3/21 m28256
mode e g w dq0 - dq7 read v il v il v ih data out write v il v ih v il data in standby / write inhibit v ih x x hi-z write inhibit x x v ih data out or hi-z write inhibit x v il x data out or hi-z output disable x v ih x hi-z notes: 1. x = v ih or v il. table 3. operating modes (1) the devices offer fast access time with low power dissipation and requires a 5v or 3v power supply. the circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with data polling and toggle bit and access to a status register. the devices support a 64 byte page write operation. a software data protection (sdp) is also possible using the standard jedec algorithm. pin description addresses (a0-a14). the address inputs select an 8-bit memory location during a read or write operation. chip enable (e). the chip enable input must be low to enable all read/write operations.when chip enable is high, power consumption is reduced. output enable (g). the output enable input con- trols the data output buffers and is used to initiate read operations. data in/ out (dq0- dq7). data is written to or read from the memory through the i/o pins. write enable (w). the write enable input controls the writing of data to the memory. operations write protection in order to prevent data corruption and inadvertent write operations; an internal v cc comparatorinhib- its write operations if v cc is below vwi (see table 7 andtable 9).access to the memoryin write mode is allowed after a power-up as specified in table 7 and table 9. read the device is accessed like a static ram. when e and g are low with w high, the data addressed is presented on the i/o pins. the i/o pins are high impedance when either g or e is high. write write operations are initiated when both w and e are low and g is high.the device supports both e and w controlled write cycles. the address is latched by the falling edge of e or w which ever occurs last and the data on the rising edge of e or w which ever occurs first. once initiated the write operation is internally timed until completion and the status of the data polling and the toggle bit functions on dq7 and dq6 is controlled accord- ingly. page write page write allows up to 64 bytes within the same page to be consecutively latched into the memory prior to initiating a programming cycle. all bytes must be located in a single page address, that is a14-a6 must be the same for all bytes; if not, the page write instruction is not executed. the page write can be initiated by any byte write operation. a page write is composed of successive write instructions which have to be sequenced with a specific period of time between two consecutive write instructions, period of time which has to be smaller than the t whwh value (see table 12 and table 13). if this period of time exceeds the t whwh value, the internal programmingcycle will start. once initiated the write operation is internally timed until comple- tion and the status of the data polling and the toggle bit functions on dq7 and dq6 is controlled accordingly. description (cont'd) 4/21 m28256
status register the devices provide several write operation status flags that can be used to minimize the application write time. these signals are available on the i/o port bits during programming cycle only. data polling bit (dq7). during the internal write cycle, any attempt to read the last byte written will produce on dq7 the complementary value of the previously latched bit. once the write cycle is fin- ished the true logic value appears on dq7 in the read cycle. toggle bit (dq6). the devices offer another way for determining when the internal write cycle is completed. during the internal erase/write cycle, dq6 will toggle from o0o to o1o and o1o to o0o (the first read value is o0o) on subsequent attempts to read any byte of the memory. when the internal cycle is completed the toggling will stop and the data read on dq7-dq0 is the addressed memory byte. the device is now accessible for a new read or write operation. page load timerstatus bit(dq5). duringa page write instruction, the devices expect to receive the stream of data with a minimum period of time between each data byte. this period of time (t whwh ) is defined by the on-chip page load timer which running/overflow status is available on dq5. dq5 low indicates that the timer is running, dq5 high indicates the time-out after which the internal write cycle will start. software data protection the devices offer a software controlled write pro- tection facility that allows the user to inhibit all write modes to the device. this can be useful in protect- ing the memory from inadvertent write cycles that may occur due to uncontrolledbus conditions. the devices are shipped as standardin the ounpro- tectedo state meaning that the memory contents can be changed as required by the user. after the software data protection enable algorithm is is- sued, the device enters the oprotect modeo of operation where no further write commands have any effect on the memory contents. the devices remain in this mode until a valid software data protection (sdp) disable sequence is received whereby the device reverts to its oun- protectedo state. the software data protection is fully non-volatile and is not changed by power on/off sequences. to enable the software data protection (sdp) the device requires the user to write (with a page write addressing three specific data bytes to three specific memorylocations,each location in a different page) as per figure 6. simi- larly to disable the software data protection the user has to write specific data bytes into six differ- ent locations as per figure 5 (with a page write adressing different bytes in different pages). this complexseries ensures that the userwill never enable or disable the software data protection accidentally. to write into the devices when sdp is set, the sequence shown in figure 6 must be used. this sequence provides an unlock key to enable the write action, and at the same time sdp continues to be set. an extension to this is where sdp is required to be set, and data is to be written. using the same sequence as above, the data can be written and sdp is set at the same time, giving both these actions in the same write cycle (t wc ). dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 dp tb plts x x x x x dp = data polling tb = toggle bit plts = page load timer status figure 4. status bit assignment 5/21 m28256
ai01698b write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h sdp is set write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h write data to be written in any address sdp enable algorithm page write instruction page write instruction write is enabled sdp set sdp not set write in memory write data + sdp set after twc figure 5. software data protection enable algorithm and memory write ai01699b write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h unprotected state after twc (write cycle time) write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write instruction figure 6. software data protection disable algorithm 6/21 m28256
input rise and fall times 20ns input pulse voltages (m28256) 0.4v to 2.4v input pulse voltages (m28256-w) 0v to v cc 0.3v input and output timing ref. voltages (m28256) 0.8v to 2.0v input and output timing ref. voltages (m28256-w) 0.5 v cc table 4. ac measurement conditions ai02101b 4.5v to 5.5v operating voltage 2.7v to 3.6v operating voltage v cc 0.3v 0v 0.5 v cc 2.4v 0.4v 2.0v 0.8v figure 7. ac testing input output waveforms ai02102b out c l = 100pf c l includes jig capacitance i ol device under test i oh figure 8. ac testing equivalent load circuit symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested. table 5. capacitance (1) (t a =25 c, f = 1 mhz ) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 10 m a i lo output leakage current 0v v in v cc 10 m a i cc (1) supply current (ttl inputs) e = v il ,g=v il ,f=5mhz 30 ma supply current (cmos inputs) e = v il ,g=v il ,f=5mhz 25 ma i cc1 (1) supply current (standby) ttl e = v ih 1ma i cc2 (1) supply current (standby) cmos e > v cc 0.3v 100 m a v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = 400 m a 2.4 note: 1. all i/o's open circuit. table 6. read mode dc characteristics for m28256 (t a = 0 to 70 c or 40 to 85 c; v cc = 4.5v to 5.5v) 7/21 m28256
symbol parameter min max unit t pur time delay to read operation 1 m s t puw time delay to write operation (once v cc v wi )5ms v wi write inhibit threshold 3.0 4.2 v note: 1. sampled only, not 100% tested. table 7. power up timing for m28256 (1) (t a = 0 to 70 c or 40 to 85 c; v cc = 4.5v to 5.5v) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 10 m a i lo output leakage current 0v v in v cc 10 m a i cc (1) supply current (cmos inputs) e=v il ,g=v il , f = 5 mhz, v cc = 3.3v 15 ma e=v il ,g=v il , f = 5 mhz, v cc = 3.6v 15 ma i cc2 (1) supply current (standby) cmos e > v cc 0.3v 20 m a v il input low voltage 0.3 0.6 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.2 v cc v v oh output high voltage i oh = 400 m a 0.8 v cc v note: 1. all i/o's open circuit. table 8. read mode dc characteristics for m28256-w (t a = 0 to 70 c or 40 to 85 c; v cc = 2.7v to 3.6v) symbol parameter min max unit t pur time delay to read operation 1 m s t puw time delay to write operation (once v cc v wi )10ms v wi write inhibit threshold 1.5 2.5 v note: 1. sampled only, not 100% tested. table 9. power up timing for m28256-w (1) (t a = 0 to 70 c or 40 to 85 c; v cc = 2.7v to 3.6v) 8/21 m28256
symbol alt parameter test condition m28256 unit -90 -12 -15 -20 min max min max min max min max t avqv t acc address valid to output valid e=v il ,g= v il 90 120 150 200 ns t elqv t ce chip enable low to output valid g=v il 90 120 150 200 ns t glqv t oe output enable low to output valid e=v il 40 45 50 50 ns t ehqz (1) t df chip enable high to output hi-z g=v il 0 40 0 45 0 50 0 50 ns t ghqz (1) t df output enable high to output hi-z e=v il 0 40 0 45 0 50 0 50 ns t axqx t oh address transition to output transition e=v il ,g=v il 0000ns note: 1. output hi-z is defined as the point at which data is no longer driven. table 10. read mode ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 4.5v to 5.5v) symbol alt parameter test condition m28256-w unit -12 -15 -20 -25 min max min max min max min max t avqv t acc address valid to output valid e=v il ,g= v il 120 150 200 250 ns t elqv t ce chip enable low to output valid g=v il 120 150 200 250 ns t glqv t oe output enable low to output valid e=v il 45 70 80 100 ns t ehqz (1) t df chip enable high to output hi-z g=v il 0 45 0 50 0 55 0 60 ns t ghqz (1) t df output enable high to output hi-z e=v il 0 45 0 50 0 55 0 60 ns t axqx t oh address transition to output transition e=v il ,g=v il 0000ns note: 1. output hi-z is defined as the point at which data is no longer driven. table 11. read mode ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 2.7v to 3.6v) 9/21 m28256
symbol alt parameter test condition m28256 unit min max t avwl t as address valid to write enable low e = v il ,g=v ih 0ns t avel t as address valid to chip enable low g = v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g = v ih 0ns t ghwl t oes output enable high to write enable low e=v il 0ns t ghel t oes output enable high to chip enable low w = v il 0ns t wlel t wes write enable low to chip enable low g = v ih 0ns t wlax t ah write enable low to address transition 50 ns t elax t ah chip enable low to address transition 50 ns t wldv t dv write enable low to input valid e = v il ,g=v ih 1 m s t eldv t dv chip enable low to input valid g = v ih ,w=v il 1 m s t eleh t wp chip enable low to chip enable high 50 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0ns t ehgl t oeh chip enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 100 ns t wlwh t wp write enable low to write enable high 50 ns t whwh t blc byte load repeat cycle time 0.15 150 m s t whrh t wc write cycle time 5 ms t el ,t wl e or w input filter pulse width note 1 10 ns t dvwh t ds data valid before write enable high 50 ns t dveh t ds data valid before chip enable high 50 ns note: 1. characterized only but not tested in production. table 12. write mode ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 4.5v to 5.5v) 10/21 m28256
symbol alt parameter test condition m28256-w unit min max t avwl t as address valid to write enable low e = v il ,g=v ih 0ns t avel t as address valid to chip enable low g = v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g = v ih 0ns t ghwl t oes output enable high to write enable low e=v il 0ns t ghel t oes output enable high to chip enable low w = v il 0ns t wlel t wes write enable low to chip enable low g = v ih 0ns t wlax t ah write enable low to address transition 70 ns t elax t ah chip enable low to address transition 70 ns t wldv t dv write enable low to input valid e = v il ,g=v ih 1 m s t eldv t dv chip enable low to input valid g = v ih ,w=v il 1 m s t eleh t wp chip enable low to chip enable high 100 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0ns t ehgl t oeh chip enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 100 ns t wlwh t wp write enable low to write enable high 100 ns t whwh t blc byte load repeat cycle time 0.2 150 m s t whrh t wc write cycle time 5 ms t el ,t wl e or w input filter pulse width note 1 10 ns t dvwh t ds data valid before write enable high 50 ns t dveh t ds data valid before chip enable high 50 ns note: 1. characterized only but not tested in production. table 13. write mode ac characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 2.7v to 3.6v) 11/21 m28256
note: write enable (w) = high. ai01700 valid tavqv taxqx tglqv tehqz tghqz data out a0-a14 e g dq0-dq7 telqv hi-z figure 9. read mode ac waveforms ai01701 valid tavwl a0-a14 e g dq0-dq7 data in w twlax telwl tghwl twldv twheh twhgl twlwh twhwl twhdx tdvwh figure 10. write mode ac waveforms - write enable controlled 12/21 m28256
ai01702 valid tavel a0-a14 e g dq0-dq7 data in w telax tghel twlel teldv tehgl tehdx tdveh teleh tehwh figure 11. write mode ac waveforms - chip enable controlled ai01703b a0-a14 e g dq0-dq7 w twhwh addr 0 dq5 addr 1 addr 2 addr n twhwh twhrh twlwh twhwl byte 0 byte 1 byte 2 byte n byte n figure 12. page write mode ac waveforms - write enable controlled 13/21 m28256
ai01704 a0-a5 e g dq0-dq7 w twlwh tdvwh byte 0 twhwl a6-a14 twlax twhwh twhdx tavel 5555h 2aaah 5555h byte 62 byte 63 aah 55h a0h byte address page address figure 13. software protected write cycle waveforms note: a6 through a14 must specify the same page address during each high to low transition of w (or e) after the software code has been entered. g must be high only when w and e are both low. ai01705 a0-a14 e g dq7 w dq7 dq7 dq7 dq7 dq7 ready last write internal write sequence address of the last byte of the page write instruction figure 14. data polling waveform sequence 14/21 m28256
ai01706 a0-a14 e g dq6 w ready last write internal write sequence (1) toggle dq6 dq6 figure 15. toggle bit waveform sequence note: 1. first toggle bit is forced to '0'. 15/21 m28256
ordering information scheme speed 90 (1) 90ns 12 120ns 15 150ns 20 200ns 25 (2) 250ns operating voltage blank 4.5v to 5.5v w 2.7v to 3.6v package bs pdip28 ka plcc32 ms so28 300 mils ns tsop28 8 x 13.4mm temperature range 1 (3) 0to70 c 6 40 to 85 c option t tape & reel packing example: m28256 15 w ka 6 t notes: 1. not available for owo operating voltage. 2. available for owo operating voltage only. 3. temperature range on request only. devices are shipped from the factory with the memory content set at all o1'so (ffh). for a list of available options (speed, package, etc...) or for further informationon any aspect of this device, please contact the stmicroelectronics sales office nearest to you. 16/21 m28256
pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2 symb mm inches typ min max typ min max a 5.08 0.200 a1 0.38 0.015 a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 0.060 c 0.20 0.30 0.008 0.012 d 36.83 37.34 1.450 1.470 d2 33.02 1.300 e 15.24 0.600 e1 13.59 13.84 0.535 0.545 e1 2.54 0.100 ea 14.99 0.590 eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.08 0.070 0.082 a 0 10 0 10 n28 28 drawing is not to scale. pdip28 - 28 pin plastic dip, 600 mils width 17/21 m28256
plcc d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 symb mm inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 0.050 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n32 32 nd 7 7 ne 9 9 drawing is not to scale. plcc32 - 32 lead plastic leaded chip carrier, rectangular 18/21 m28256
so-b e n cp b e a2 d c l a1 a h a 1 symb mm inches typ min max typ min max a 2.46 2.64 0.097 0.104 a1 0.13 0.29 0.005 0.011 b 0.35 0.48 0.014 0.019 c 0.23 0.32 0.009 0.013 d 17.81 18.06 0.701 0.711 e 7.42 7.59 0.292 0.299 e 1.27 0.050 h 10.16 10.41 0.400 0.410 l 0.61 1.02 0.024 0.040 a 0 8 0 8 n28 28 cp 0.10 0.004 drawing is not to scale. so28 - 28 lead plastic small outline, 300 mils body width 19/21 m28256
symb mm inches typ min max typ min max a 1.25 0.049 a1 0.20 0.008 a2 0.95 1.15 0.037 0.045 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 13.20 13.60 0.520 0.535 d1 11.70 11.90 0.461 0.469 e 7.90 8.10 0.311 0.319 e 0.55 - - 0.022 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n28 28 cp 0.10 0.004 drawing is not to scale. tsop28 - 28 lead plastic thin small outline, 8 x 13.4mm tsop-c d1 e 78 cp b e a2 a 22 d die c l a1 a 21 28 1 20/21 m28256
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. spec ifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 21/21 m28256

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